1. Field of the System
The present system relates to field programmable gate array (FPGA) devices. More specifically, the system relates to an apparatus for interfacing and testing a phase locked loop of an FPGA.
2. Background
FPGAs are known in the art. An FPGA comprises any number of logic modules, an interconnect routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. To implement a particular circuit function, the circuit is mapped into an array and appropriate connections are programmed to implement the necessary wiring connections that form the user circuit.
A gate array circuit can be programmed to implement virtually any set of functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers. Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis.
An FPGA core tile may be employed as a stand-alone FPGA, repeated in a rectangular array of core tiles within a single integrated circuit, or included with other devices in a system-on-a-chip (SOC). The core FPGA tile may include an array of logic modules, and input/output modules. An FPGA core tile may also include other components such as read only memory (RAM) modules. Horizontal and vertical routing channels provide interconnections between the various components within an FPGA core tile. Programmable connections are provided by programmable elements coupled between the routing resources.
As FPGAs grow in size, on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact FPGA performance and the task of managing clock skew and clock delay with conventional clock trees becomes more difficult in large FPGAs. As such, in large, fast FPGAs, the performance limiting element is often clock delay due to large clock networks. Phase locked loops (PLLs) are used to reduce the clock delays inherent in large FPGAs and, thereby improve performance.
FIG. 1 is a simplified diagram illustrating two internal clock tree branches. This is known to those skilled in the art as an “H tree” clock distribution scheme. The goal of a PLL is to minimize clock skew by having near equal delay in each branch of the clock network. As the FPGA grows, the number of branches is increased, and buffer sizes are tuned to equalize the delay between branches.
FIG. 2 shows the relationship between total clock delay and skew, or the difference in delay between the branches in the clock tree. Both total clock delay and clock skew are factors in high performance systems.
By anticipating the edges of the input clock, a PLL can generate new clocks with edges slightly earlier than the input clock. By tuning the amount of time these new clock edges precede the input clock edge to the delays of the various clock tree branches, all registers will see the clock edge at about the same time. This reduces the overall clock network delay as well as minimizing clock skew.
FIG. 3 is a simplified diagram illustrating the timing of a clock network using a PLL. As shown in FIG. 3, the internal clock (dotted lines) are being generated ahead of the input clock, so the internal clocks arrive at their destinations much closer to the input clock edge. Some clock skew still occurs due to the delay in each branch, however overall performance is improved by using a PLL.
Hence, PLLs are important tools to increase performance in large, fast FPGAs. There is need in the art for an apparatus for interfacing and testing PLLs in an FPGA.